Intel's being cautious on ramping up 14A wafers until it knows that it has enough customers

But it's full steam ahead on its other process nodes.
EDN

3-D wafer process combines benefits of Si, GaAs, InP

Semiconductor manufacturer Xanoptix (Merrimack, NH) has developed a wafer-scale process for the 3-D stacking of silicon with either GaAs or InP to make compound semiconductors. The company's Hybrid ...
VentureBeat

Cerebras' wafer-size chip is 10,000 times faster than a GPU

Cerebras Systems and the federal Department of Energy's National Energy Technology Laboratory today announced that the company's CS-1 system is more than 10,000 times faster than a graphics processing ...
Semiconductor Engineering

How Guardbanding Of Inline Wafer Defects Can Improve Chip Reliability Insurance

Partially defective, marginal die can still be functional enough to pass final electrical test. Some of these “walking wounded” chips get past final testing, but in the customer’s end product, under ...

Lam Research: Winning As Chips Go Vertical

Lam Research powers AI chipmaking with leading etch/deposition tools and recurring service revenue. Click here to find out ...
TweakTown

Apple iPhone 18 with A20 chip could switch to wafer-level multi-chip module packaging

TL;DR: Apple's iPhone 18 will feature the next-gen A20 chip using TSMC's advanced WMCM packaging with MUF technology, enhancing efficiency and yield. Eternal secured a major contract as a packaging ...